A content addressable memory (CAM) may be described as a device in which a binary data input pattern is compared with stored data patterns to find a matching binary pattern. When the CAM detects such a match, it provides an address or location (called a match address). It is known in some system architectures for a CAM to scan a random address memory (RAM) cell to find the matching data pattern, and such a structure and method is known as a CAMRAM memory array.
The present invention relates to CAMRAM memory array structures, and in particular to CAMRAM""s on Application Specific Integrated Circuit (ASIC) chip micro-controller processor cores. It is known to use CAM and RAM structures, singly or in combination, to provide a xe2x80x9credundancy functionxe2x80x9d in ASIC applications. A redundancy function may be utilized when a program driving the ASIC identifies defective row addresses. The redundancy function selects and provides a replacement row of good addresses, and a corrected matchline/wordline association is created.
ASIC applications are being designed with progressively increasing sizes of memory elements, but upon a progressively decreasing silicon device geometry, and accordingly more and more imperfect ASIC chips are produced. What is needed is a method and structure that will improve manufacturing yield while meeting the ASIC design demands. With the increasing size of memory elements, along with the requirement of faster access time and smaller available areas on ASIC chips, improved architecture of the CAMRAM base design is desired to address these issues effectively. What is also needed is a redundant scheme for a CAMRAM that will improve manufacturing yield and not result in any extra performance penalty in the operation of the ASIC.
A content addressable memory (CAM) structure and method that provides a redundant scheme for an ASIC. The scheme comprises a CAM comparative means for bypassing normal encoders including a fuse structure having a fuse address list and a xe2x80x9cCAM row comparexe2x80x9d structure. Redundancy is provided in xe2x80x9cCAM Search Readxe2x80x9d and xe2x80x9cCAM Search Read and RAM Readxe2x80x9d operations. Normal CAM memory address rows and redundant replacement CAM memory address rows are provided for bank addresses. A miss logic is provided for detecting a bank address miss and generating a responsive miss signal, and an xe2x80x9caddress outxe2x80x9d logic is also provided to pass only one of a generated normal CAM memory address row, redundant replacement address row or miss signal in a bank. The method and structure can support different address sizes and different cache sizes, allowing user versatility in design and application. Accordingly, the present invention offers advantages in improved manufacturing yields, performance and portability.